An ASIC is developed and optimized for a specific application and cannot be reconfigured. Its internal circuit elements (transistors) are arranged in a fixed structure with fixed and unchangeable interconnect (wiring) in between.   

Because an ASIC serves only one purpose, it incorporates only the logic elements that are necessary for that purpose; for example, if a floating-point multiplier is not needed, then it is not incorporated into the design. 

Conversely, an FPGA may be configured and reconfigured for any potential applications. Like an ASIC, its internal circuit elements are arranged in a fixed structure (programmable logic blocks or PLBs) but with reconfigurable interconnects in between. The logic elements in an FPGA are selected to support a wide variety of applications but suffer from “use it or lose it” when specific logic elements are not used. If a floating-point multiplier is not required for a particular application, but the FPGA contains one, then that resource is unconnected and represents “wasted space” within the FPGA.

While both devices can contain hundreds of millions of transistors, an ASIC can use those transistors to deliver high efficiency and performance at the expense of flexibility. The upfront NRE charges to develop an ASIC can be exorbitant, while the unit costs can be relatively low. 

An FPGA uses its transistors to deliver high efficiency and high performance but with tremendous flexibility. The upfront NRE charges to develop an FPGA can be extremely low, while the unit costs are generally higher. It is important to note that these are not hard and fast rules. In the performance arena, for example, recent FPGAs have evolved to deliver clock rates of more than 500 MHz and are generally fabricated at state-of-the-art silicon process geometries. In short, the boundary between FPGAs and ASIC becomes increasingly fuzzy with each new FPGA generation.

Specific FPGA-based functions, as well as the interconnects between those functions, are “described” in an HDL. The description is compiled to produce an FPGA configuration file. Using a hardware description language, it is possible to use built-in FPGA resources (memory arrays, PCI cores and many more), as well as to create customized logic circuits (adders, multiplexers and other application-specific functions) from more primitive FPGA elements.

In a process known as synthesis, the HDL code is translated into a netlist, an effective description of the logic gates and interconnects needed to implement the HDL code. The netlist is then mapped onto the PLBs and interconnects that physically form the unique circuit.

Modern FPGAs produced by manufacturers like Intel and Altera offer a wide range of digital and analog features, including impressive logic densities, flash memory, embedded processors and digital signal processing (DSP) blocks. FPGAs can be configured and reconfigured by modifying electrical inputs and outputs, choosing which internal resources are used and determining how these resources are connected through configurable routing resources—the end result being a dedicated hardware solution to solve a particular problem.

As with software, the development of complex FPGA designs might be streamlined by using pre-designed libraries of various functions and digital circuits, referred to as intellectual property (IP) cores. These libraries are available for purchase or lease from FPGA vendors and third-party suppliers who often specialize in developing various functions.

These programmable elements are primarily configurable logic blocks (CLBs), programmable interconnects, programmable routing, programmable input/output blocks (IOBs), on-chip memory and digital signal processing blocks (DSPs). 

Configurable logic blocks (CLBs) are the primary component of FPGAs. CLBs generally contain a few primitive logic elements (logic gates, small look-up tables, flip-flops, multiplexers and many more). Within the CLB, a flip-flop generally serves as the main data storage element, although newer device families might also incorporate shallow memory elements within the CLB.

Linkages constructed from wire segments joined by electrically programmable switches provide routing pathways between the FPGA’s logic block. Switch boxes containing multiple basic semiconductor switches are commonly used to establish an FPGA’s programmable interconnect. These interconnects allow the outputs of a specific unit or an input pad to be linked to any other cell or pad within the circuitry.

Prefabricated wire segments are joined together (or left unconnected) by the programmable interconnects to deliver a fully programmable routing infrastructure within an FPGA. Routing resources are hierarchical in nature, with a combination of long, medium and short wires spanning various “lengths” within the FPGA.  This programmable routing infrastructure, enabled by the programmable interconnects, allows users to configure FPGA resources for the implementation of a particular task or application.

The interface between an FPGA and other external devices is enabled by input/output (I/O) blocks (IOBs). IOBs are programmable input and output resources that are configured to match the protocols of any external devices to which the FPGA connects. All signals entering or leaving the FPGA do so through device pins and associated IOBs.

The earliest FPGAs used only flip-flops (FFs) to integrate memory into the FPGA logic blocks. However, as FPGA capabilities increased, increasingly complex designs required dedicated on-chip memory for data buffering and reuse. Modern FPGAs use large SRAM memory arrays, smaller look-up tables (LUTs) and traditional flip-flop elements to provide the necessary storage for a specific application.

In early FPGAs, the sole available arithmetic resources were simple adders; anything more complex was constructed from more primitive logic elements. However, as silicon technology advanced, more complex arithmetic resources were incorporated into FPGAs, culminating in the modern FPGA DSP block. DSP blocks provide highly optimized resources (multipliers, accumulators and many more) for the implementation of high-performance arithmetic functions. Their use eliminates the need to implement these functions in general-purpose CLBs, hence freeing up the CLBs for other purposes. Operations like digital filtering, convolution, Fourier transforms, trigonometric operations and many more can take advantage of these resources to obtain real-time performance in applications ranging from radar processing, beamforming, pattern recognition and many more.

• Antifuse-based FPGAs: FPGAs that are configurable but not reconfigurable. They use a one-time programmable element called an antifuse, which is configured by applying a high voltage to create connections between internal wires. An antifuse-based FPGA can only be configured once and cannot be reconfigured.
• SRAM-based FPGAs: These types of FPGAs are highly versatile and can be configured at run time. SRAM-based FPGAs use static random-access memory (SRAM) to store their configuration instructions and require external memory to hold the configuration code.
• Flash-based FPGAs: Unlike SRAM-based FPGAs, flash-based FPGAs store their configuration in nonvolatile flash memory, which has the added benefit of being reprogrammable.
• EEPROM-based FPGAs: This variety of FPGA is similar to flash-based FPGAs, but electronically erasable programmable read-only memory (EEPROM) stores the FPGA’s configuration. Both styles are nonvolatile and are reprogrammable.
• Hybrid FPGAs: Hybrid FPGAs provide varying levels of performance, low-power operation and versatility through a combination of different programmable elements, such as SRAM- or flash-based logic blocks.
• System-on-chip FPGAs: System-on-chip (SoC) FPGAs integrate programmable logic with hard processor cores, combining the functionality of both an FPGA and an SoC, a single silicon chip that combines multiple system processing chips like CPUs, GPUs and RAM into one unit.