APAR status
Closed as program error.
Error description
Error Message: A SIGSEV in findHelperTrampoline() was encountered by the customer reporting the problem. The problem can result in a SIGSEGV while executing in any of the following methods: TR_MCCManager::replaceTrampoline() TR_MCCManager::findCodeCacheFromPC() TR_MCCManager::addFreeBlock() TR_MCCManager::freeFaintCacheBlock() mcc_callPointPatching_unwrapper() mcc_reservationAdjustment_unwrapper() TR_MCCManager::reservationInterfaceCache() TR_MCCManager::findMethodTrampoline() TR_MCCManager::findHelperTrampoline() . Stack Trace: TR_MCCManager::findHelperTrampoline(void*,int)() TR_J9VMBase::indexedTrampolineLookup(int,void*)() TR_PPCCallSnippet::emitSnippetBody()() TR_PPCUnresolvedCallSnippet::emitSnippetBody()() TR_Snippet::emitSnippet()() TR_CodeGenerator::emitSnippets(bool)() TR_CodeGenerator::generateCode()() TR_Compilation::generateCode()() . This problem can only occur on POWER (PPC) based hardware. The changes of hitting this problem is very small. The timing window where this problems exists is extremely short and the frequency of executing the code path where the problem can occur is rare.
Local fix
The problem can NOT be avoided completely but the the chances of hitting the problem can be greatly reduced by reducing the number of code cache allocations and/or by limiting the JIT to one compiler thread. The problem exists (and is fixed by this APAR) in Java 6.0 but the chances of hitting the problem in that release is almost non-existent. Work-around for Java 6.1 (J9 26), 7.0, 7.1 and 8.0. 1. Reduce the frequency of code cache allocations by allocating larger code caches: -Xcodecache8m 2. Limiting the JIT compiler to only one thread: -XcompilationThreads1 Application ramp-up time will be negatively effected by reducing the number of compilation threads but increasing the default code-cache size should have no negative effect on performance.
Problem summary
The POWER CPU has week memory coherency which means that in a multiple CPU environment the visibility of 2 memory writes is not guaranteed to be visible on other threads in the same order, the 2nd write could be visible before the 1st write. The JIT maintains a linked list of allocated code-caches which is susceptible to a SIGSEGV when a thread is adding to the list at the same time as another thread is scanning the list.
Problem conclusion
The JIT was modified so that a "sync" instruction is issued when adding code-caches to the linked list such that the visibility of the new code-cache structure is insured before the list is updates to include the new code-cache. . This APAR will be fixed in the following Java Releases: 7 R1 SR3 FP20 (7.1.3.20) 7 SR9 FP20 (7.0.9.20) 8 SR2 (8.0.2.0) 6 R1 SR8 FP15 (6.1.8.15) 6 SR16 FP15 (6.0.16.15) . Contact your IBM Product's Service Team for these Service Refreshes and Fix Packs. For those running stand-alone, information about the available Service Refreshes and Fix Packs can be found at: https://www.ibm.com/developerworks/java/jdk/
Temporary fix
Comments
APAR Information
APAR number
IV76414
Reported component name
JIT
Reported component ID
620700124
Reported release
130
Status
CLOSED PER
PE
NoPE
HIPER
NoHIPER
Special Attention
NoSpecatt
Submitted date
2015-08-27
Closed date
2015-09-01
Last modified date
2015-09-01
APAR is sysrouted FROM one or more of the following:
APAR is sysrouted TO one or more of the following:
Fix information
Fixed component name
JIT
Fixed component ID
620700124
Applicable component levels
R130 PSY
UP
R260 PSY
UP
R600 PSY
UP
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Document Information
Modified date:
01 September 2015