SS format

The operand fields and subfields of SS-format instructions designate two virtual storage addresses (coded as implicit addresses or explicit addresses) and, optionally, the explicit data lengths you want to include. However, in the Shift and Round Decimal (SRP) instruction, a 4 bit immediate data field (see the operand 3 in the example of an SRP instruction), with a value 0 - 9, is specified as a third operand.
Diagram showing the operand fields and subfields of SS-format instructions.
Diagram showing the operand fields and subfields of SS-format instructions.
Diagram showing the operand fields and subfields of SS-format instructions.
Diagram showing the operand fields and subfields of SS-format instructions.
Diagram showing the operand fields and subfields of SS-format instructions.

Symbols used to represent base registers (see BASE8 and BASE7 in the instruction labeled ALPHA2 in the examples) in explicit addresses are assumed to be equated to absolute values 0 - 15.

Symbols used to represent explicit lengths (see NINE and SIX in the instruction labeled ALPHA2 in the examples) are assumed to be equated to absolute values 0 - 256 for SS-format instructions with one length specification, and 0 - 16 for SS-format instructions with two length specifications.

Symbols used to represent implicit addresses (see FIELD1 and FIELD2 in the instruction labeled ALPHA3, and FIELD1,X'8' in the SRP instructions in the examples) can be either relocatable or absolute.

Symbols used to represent displacements (see DISP40 and DISP30 in the instruction labeled ALPHA5 in the examples) in explicit addresses are assumed to be equated to absolute values 0 - 4095.

See topic Lengths for more information about the lengths of SS-format instructions.

Examples:
ALPHA1   AP              40(9,8),30(6,7)
ALPHA2   AP              40(NINE,BASE8),30(SIX,BASE7)
ALPHA3   AP              FIELD1,FIELD2
ALPHA4   AP              AREA(9),AREA2(6)
ALPHA5   AP              DISP40(,8),DISP30(,7)
BETA1    MVC             0(80,8),0(7)
BETA2    MVC             DISP0(,8),DISP0(7)
BETA3    MVC             TO,FROM
         SRP             FIELD1,X'8',3
When assembled, the object code for the instruction labeled ALPHA1, in hexadecimal, is:
FA858028701E
where:
FA
Is the operation code.
8
Is length L₁
5
Is length L₂
8
Is base register B₁
028
Is displacement D₁ from base register B₁
7
Is base register B₂
01E
Is displacement D₂ from base register B₂
When assembled, the object code for the instruction labeled BETA1, in hexadecimal, is:
D24F80007000
where:
D2
Is the operation code
4F
Is length L
8
Is base register B₁
000
Is displacement D₁ from base register B₁
7
Is base register B₂
000
Is displacement D₂ from base register B₂