Header/self-defining section, based on the address of SMF record type 113 + the offset value in SMF113DOF

This section contains the common SMF subtype header fields and the triplet fields (offset/length/number), if applicable, that locate the other sections on the record.

Offsets		Name	Length	Format	Description
0	0	SMF113_1_CTS	8	binary	Time when the hardware data collection run started in STCK format
8	8	SMF113_1_CTM	8	binary	Time when this SMF record was written in STCK format.
16	10	SMF113_1_CpuId	2	binary	Processor ID for which the hardware counters are recorded. Note that zero is a valid processor number.
18	12	SMF113_1_CpuProcClass	1	binary	The processor type for which the hardware event counters are recorded. Is one of the following: 0 Standard CP 2 zAAP 4 zIIP
19	13		1	binary	Reserved.
20	14	SMF113_1_CpuSpeed	4	binary	Processor speed for which the event counters are recorded. Speed is in cycles/microsecond.
24	18	SMF113_1_MachType	4	EBCDIC	The machine type.
28	1C	SMF113_1_MachModel	16	EBCDIC	The machine model.
44	2C	SMF113_1_CtrVersion0	2	binary	Zero counter version number. This number is increased when there is a change to the meaning of a counter in the z/OS® counter set.
46	2E	SMF113_1_CtrVersion1	2	binary	First counter version number. This number is increased when there is a change to the meaning of a counter or the number of installed counters in the Basic or Problem-state counter sets.
48	30	SMF113_1_CtrVersion2	2	binary	Second counter version number. This number is increased when there is a change to the meaning of a counter or the number of installed counters in the Crypto-activity or Extended or MT-diagnostic counter sets.
50	32	SMF113_1_Flags2	2	binary	Record flags: Bit Meaning when set 0 The hardware indicated the hardware has lost counter data during the current interval. 1 The hardware indicated the hardware has lost MT counter data during the current interval.
Self-defining section
52	34	SMF113_1_CSOF	4	binary	Offset to counter set section, from beginning of r SMF record type 113.
56	38	SMF113_1_CSLN	2	binary	Length of counter set section.
58	3A	SMF113_1_CSON	2	binary	Number of counter set sections.
60	3C	SMF113_1_SeqCode	16	EBCDIC	The machine sequence code.
76	4C	SMF113_1_CoreId	2	binary	Core ID for which the hardware event counters are recorded. Note that zero is a valid core ID number.